1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to technology for dual structure antifuse technology in which a planar gate and a buried gate are formed.
2. Related Art
In recent years, with the rapid spread of information media such as computers, semiconductor devices have been developed to operate the information media. In terms of function, desirable characteristics of semiconductor devices include high-speed operation and large storage capacity. Thus, fabrication technology of the semiconductor devices have been developed to improve integration, reliability, and response speed.
Existing methods of fabricating semiconductor devices include a fabrication (FAB) process which repeatedly forms preset circuit patterns on a substrate which is typically formed of a silicon material to form cells having integrated circuits, and an assembly process which packages the substrate in which the cells are formed in units of chips. An electrical die sorting (EDS) process for testing electrical characteristics of the cells may be performed before assembly.
The EDS process determines whether the cells formed on the substrate are in an electrically good state or in a failed state. The cells in the failed state are removed during the EDS process before the assembly process is performed to improve cost and efficiency. In addition, defective cells may be detected in advance and then repaired through a repair process.
Hereinafter, the repair process will be described.
Redundant cells are added to a semiconductor device, and may be used to replace failed circuits to improve yields. Fuses are designed to disconnect the failed cells in an integrated circuit. When a failed circuit is detected, a fuse may be cut to replace the failed circuit with redundant cells.
Even after the EDS repair process has been performed to repair the defected cells at the wafer level, 1-bit or 2-bit defects may occur in a device that passed the EDS test after the package process is performed. Thus, even when the EDS process is performed at the wafer level, a defect rate of, for example, about 10% may occur in packaged devices, and thus a repair process following the packaging process is performed. In particular, in multi-chip packages, dynamic random access memories (DRAMs), and relatively high-priced flash RAMs, 1-bit or 2-bit defects occurring or detected after packaging may cause a device to fail. Thus, a repair process performed on packaged devices can improve manufacturing yields and reduce the chance of shipping defective units.
However, laser repair equipment used before packaging may not be usable following the packaging process, so a repair process after packaging may use different types of fuses and techniques from the repair process prior to packaging.
Hereinafter, a fuse used in the repair process following packaging will be described.
A fuse used in the repair process following the packaging process is an antifuse. This is because the repair process prior to the packaging process is performed by cutting fuses, while the repair process following the packaging process is performed not by cutting the fuses to break an electrical connection, but by establishing an electrical connection between elements that were not previously connected. Thus, an antifuse may be a fuse which is electrically opened-circuited in a normal state, and is short-circuited when an insulator between conductors is ruptured by applying a high voltage. The antifuse is formed in a peripheral circuit area and redundant cells for the antifuse are also formed in the peripheral circuit area. The redundant cells may be static random access memories (SRAM) with non-refresh characteristics.
The antifuse enables repairs at the package level, and may be used to increase a net yield, improve product characteristics, and avoid dependence on the prior laser fuse equipment and processes.
Thus, it is important to ensure successful rupture and reliability of a gate oxide layer in an antifuse.